1. Field of the Invention
The present invention relates to an apparatus for and a method of detecting delay fault in a phase-locked loop circuit, and more particularly, relates to a delay fault detecting apparatus and a delay fault detecting method each of which is suitable for detecting a delay fault in a phase-locked loop (hereinafter referred to as PLL) circuit formed on VLSI (very large scale integrated circuit) chip.
2. Description of the Related Art
A synchronous system performs a cooperative operation by sharing a timing of a clock edge with one another. When a timing of the shared edge is controlled in higher precision, the synchronous system can operate at a higher frequency. FIG. 1 shows an example of the synchronous system. This system is configured such that a plurality of (in this example, two) VLSI chips 11 and 12 are placed on a single board (not shown). A reference clock xcfx86 is supplied to each of the VLSI chips 11 and 12 from a high precision oscillator (for example, a crystal-based clock generator) 13 provided on the board. In PLL circuits 14 and 15 on these VLSI chips, as shown in FIG. 2, clocks xcfx8611, xcfx8612, and xcfx8621, xcfx8622 generated by the on-chip clock generators are synchronized with the externally supplied reference clock xcfx86 and are distributed to subsystems 16 and 17, respectively. (For example, refer to a reference literature d1.)
As described above, by synchronizing the edge of an internal clock with respect to the edge of a reference clock, data can be sent and received freely between different chips. By aligning the frequency and the phase of an oscillation waveform of a voltage-controlled oscillator (hereinafter referred to as VCO) with respect to the frequency and the phase of the external reference clock xcfx86, the PLL circuits 14 and 15 play a role in minimizing a clock skew and ensuring a high speed operation of the system.
As is well known, in a microcomputer, the worst case uncertainty in the instantaneous value (a peak-to-peak jitter or the like) of the clock signal determines the operating frequency of the microcomputer. Accordingly, it is necessary in the microcomputer to surely detect, by testing, such a delay fault that manifest itself as a transient clock skew.
Next, an influence of delay faults in PLL circuits on a system will be discussed. FIG. 3 shows an example of the PLL circuit. This PLL circuit comprises a phase-to-frequency (phase-frequency) detector 21, a charge pump circuit 22, a loop filter 23, a VCO 24, and a clock decode and buffer circuit 25. Now, it is assumed that a delay fault DF1 is present at the reference clock input of the phase-frequency detector 21. As shown in FIG. 4, a reference clock xcfx86REF (indicated by a solid line) applied to the reference clock input of the phase-to-frequency detector 21 of the PLL circuit becomes a skew clock xcfx86 (indicated by a dotted line) which has been delayed by a constant time period due to the delay fault DF1 present at the reference clock input, and is fed into the charge pump circuit 22 of the next stage. In the PLL circuit, an edge of an internal clock xcfx861 (indicated by a solid line) is synchronized with respect to the edge of the dotted line clock xcfx86 which has been delayed by the constant time period. As a result, a clock skew occurs in response to the delay fault DF1. Moreover, the clock skew which is a deviation generated at the reference clock input is not compensated in the PLL circuit and is continued to be held at a constant value. As a result, it appears that a large steady-state deviation remains.
Since this delay fault DF1 is not a fault of an internal block (internal component) of the PLL circuit, the PLL gets into a synchronous state. Accordingly, it is difficult to detect a delay fault at the reference clock input by testing the internal blocks of the PLL circuit. However, a delay fault of this type can easily be detected by comparing the external reference clock xcfx86REF with the internal clock xcfx861.
Next, as shown in FIG. 5, it is assumed that a delay fault DF2 is present at the Up signal input of the charge pump circuit 22. Due to this delay fault DF2, a timing in the charge pump circuit 22 for converting an Up signal outputted from the phase-frequency detector 21 into an analog signal to output the converted analog signal is delayed. Moreover, the delay of the analog signal brings about a timing delay of an oscillation of the VCO 24. In the next step, the phase-frequency detector 21 compares the edge of the reference clock xcfx86REF with the edge of the internal clock xcfx861, and controls the timing of the oscillating frequency of the VCO 24 by using a phase error signal the height of which is proportional to the time interval between the rising edges of these two clock signals. The feedback control is continued until the rising edges of both the clock signals are aligned with each other. Therefore, this delay fault DF2 appears simultaneously with a state transition and is compensated by the feedback. The delay time is maximized immediately after the state transition. Therefore, as shown in FIG. 6, a clock skew is also maximized immediately after the state transition, and it is decreased to zero in multiple consecutive cycles, because a PLL circuit is a feed back system as mentioned above. Thus, a transient skew occurs. Since a time during which a skew occurs is limited, it is hard to detect the transient skew by testing.
As discussed above, when a delay fault DF1 is present at the reference clock input of the phase-frequency detector 21, a clock skew having constant time duration occurs. This clock skew is not compensated by the PLL circuit. On the other hand, when a delay fault DF2 is present at the Up signal input of the charge pump circuit 22, a large transient clock skew appears associated with a state transition shown in FIG. 7. This transient clock skew caused by the delay fault DF2 is compensated by the PLL circuit and approaches to zero. It is to be noted that all of the delay faults in the remaining blocks (in the input end of the loop filter 23 and in the input end of the VCO 24) of the PLL circuit can be mapped to the delay fault in the input end of the charge pump circuit 22.
A stuck-at fault testing (for example, refer to a reference literature d2) has conventionally been utilized most widely in the verification test and the manufacturing test of VLSI chips. First, the stuck-at fault testing will briefly be explained.
A fault model is a model in which a physical defect is abstracted. When the fault model is used, the operation of a circuit in the presence of faults can easily be simulated using a computer. For example, a state in which an output of a CMOS (complementary metal-oxide semiconductor) inverter keeps taking a logical value xe2x80x9c1xe2x80x9d can be explained by using a model in which a stuck-at 1 fault is present in the output of the inverter. As a cause of the fault of this type, there can be considered a short-circuit defect between the output of the inverter and the power supply line of VDD or a physical open defect that breaks a drain of an nMOS (n-channel metal-oxide semiconductor).
In the testing, a test pattern is applied to primary inputs of a circuit under test and a response pattern of the circuit appearing at primary outputs of the circuit under test is observed. By comparing the response pattern with an expected value pattern in fault-free operation, whether the circuit is faulty or not is checked. FIG. 8 shows a combinational circuit of a NAND gate ND1 having no stuck fault and a NAND gate ND2 having a stuck-at 0 fault (s-a-0). The outputs of both the NAND gates ND1 and ND2 are taken out through an OR gate OR1 as a primary output.
A test pattern which can detect the stuck-at 0 fault in the combinational circuit shown in FIG. 8 is xe2x80x9c110xe2x80x9d. That is, as shown in FIG. 8, it is this test pattern xe2x80x9c110xe2x80x9d that is applied to the primary inputs of the combinational circuit. When the test pattern xe2x80x9c110xe2x80x9d is applied to the primary inputs of the combinational circuit, if it is fault-free, the primary output of the combinational circuit becomes xe2x80x9c1xe2x80x9d. On the other hand, if the combinational circuit is faulty, the primary output thereof is xe2x80x9c0xe2x80x9d. Hence, by applying the test pattern xe2x80x9c110xe2x80x9d to the combinational circuit, it is possible to identify whether a fault is present in the combinational circuit under test or not. Further, when the value of the test pattern is carefully observed, it can be seen that this test pattern is generated such that it takes a complementary logical value xe2x80x9c1xe2x80x9d at the site of the stuck-at 0 fault.
The rapid development of processing technology is pushing integrated circuit (IC) into deep submicron so that wire delays (each caused by a signal wire when a signal propagates along the signal wire) are more significant than gate delays (each caused by a gate element when a signal propagates through the gate element). As a result, delay fault testing has begun to be used in testing of microprocessors (for example, refer to reference literature d3). Next, a conventional delay fault testing method will briefly be explained (for example, refer to a reference literature d4).
Two fault models have been proposed for delay faults, one of which is a gate delay fault and the other of which is a path delay fault. A circuit is said to have a gate delay fault if a time taken by a signal propagating through a gate in the circuit exceeds the specified worst propagation delay value. Similarly, a circuit is said to have a path delay fault if a time taken by a signal propagating along a signal path in the circuit exceeds the specified worst propagation delay value.
The delay fault testing requires two-pattern tests. FIG. 9 shows an example of the delay fault testing. The illustrated circuit under test is a combinational circuit which comprises first, second and third NAND gates ND1, ND2 and ND3 configured such that the outputs of the first and the second NAND gates ND1 and ND2 are fed into the third NAND gate ND3. First, an initializing pattern V1 is applied, using a slow clock, to primary inputs of the circuit under test. This initializing pattern V1 in this example is xe2x80x9c1111xe2x80x9d. The reason for using a slow clock is that a delay fault does not affect the state transition, if its cycle time is long enough to allow all transitions in the circuit to settle. After the circuit under test has entered into an initial state, a test pattern V2 is applied to the primary inputs of the circuit under test using a fast clock. This test pattern V2 in this example is xe2x80x9c0101xe2x80x9d. Thus, as seen on the drawing of FIG. 9, the upper lead of the two input leads of the first NAND gate ND1 (the input lead to which xe2x80x9c0xe2x80x9d of the test pattern V2 is applied), the upper lead of the two input leads of the second NAND gate ND2 (the input lead to which xe2x80x9c0xe2x80x9d of the test pattern V2 is applied), and the signal lines from the outputs of the first and second NAND gates ND1 and ND2 to the inputs of the third NAND gate ND3 are activated. Pulses corresponding to the test pattern V2 propagate through these leads and signal lines. As a result, each pulse appears at the primary output of the circuit under test (the output of the third NAND gate ND3) correspondingly to the propagation delay time. This outputted final value is captured into an output latch which is clocked by the fast clock. The latched value is used to determine whether or not a delay fault is present in the circuit under test. Usually, a system clock is used as the fast clock. FIG. 10 shows a concept of the delay fault testing described above. Input latches 31 and output latches 32 are connected to the front stage and the rear stage of the circuit under test (combinational circuit) 30, respectively.
It is very difficult to generate test patterns for a delay fault testing. The reason is that in order to detect the target delay fault independently of a delay time and all other delay faults located in a circuit, the following condition must be satisfied. That is, both xe2x80x9cthe on-path input pulse propagating through the activated line under testxe2x80x9d and xe2x80x9cthe off-path sensitizing input pulses propagating through the side-input lines which are joining to the line under testxe2x80x9d must be glitch free (for example, refer to a reference literature d5). For this reason, the conventional delay fault testing method generates test patterns for only a small number of signal lines, and hence can detect only a limited number of delay faults present in the circuit.
As VLSI circuits grow more and more in size and complexity, it becomes more difficult to align all the clock edges within a chip with respect to the reference clock edge and to distribute the clock signal with a minimum skew. For this reason, for example, an algorithm called H-tree configuration is introduced into the layout design of a clock-distribution network (wiring for distributing the clock signal). A curve called H-tree is a Hilbert curve shown in FIG. 11 (for example, refer to reference literature d6). Since, in the H-tree, all of the cells connected to leaf nodes respectively are equidistant from the clock driver, the clock skew is theoretically zero. Moreover, the Hilbert curve is self-similar and is able to construct a brain structure (three-dimensional wiring layout) (for example, refer to reference literature d7). In addition, the Hilbert curve can be generated easily using a recursive algorithm. An application of the Hilbert curve to the three-dimensional clock-distribution network or the like is an interesting field to study.
As the operation speed or rate of a VLSI circuit is increased more and more, at-speed testing of clock-distribution networks has become more important. However, the conventional delay fault testing method is not suitable for efficiently testing of clock-distribution networks.
It is difficult for the following reasons to test a delay fault in a PLL circuit 40, as shown in FIG. 12, using the aforementioned conventional delay fault testing method. First, (i) when latches are inserted in the PLL circuit 40, an additional skew is incurred in the internal clock of the PLL circuit 40. As a result, a performance penalty is inevitable, which slows down its target operating speed. Next, (ii) in order to latch an internal clock of the PLL circuit, a higher speed clock is necessary. That is, this results in a self-contradiction.
It is an object of the present invention to provide an apparatus for and a method of detecting a delay fault in a PLL circuit utilizing the slope of an instantaneous phase of an analytic signal.
In order to accomplish the above object, in an aspect of the present invention, there is provided a method of detecting a delay fault in a phase-locked loop circuit, which comprises the steps of: applying a frequency impulse to a phase-locked loop circuit to cause a state transition of the phase-locked loop circuit; estimating, from a signal outputted from the phase-locked loop circuit, an instantaneous phase of the signal; and measuring, from the fluctuation term of the instantaneous phase, a time duration during which the phase-locked loop circuit stays in a state of oscillating a certain frequency.
In a preferred embodiment, the aforesaid step of estimating an instantaneous phase includes the steps of: transforming a waveform of the output signal from the phase-locked loop circuit to an analytic signal; and estimating an instantaneous phase of the analytic signal, and the aforesaid step of measuring a time duration includes the step of: detecting a delay fault by comparing a time duration during which the phase-locked loop circuit stays in a state of oscillating a certain frequency with a time duration during which a fault-free phase-locked loop circuit having no delay fault present therein stays in a state of oscillating a certain frequency.
In addition, the aforesaid step of measuring a time duration is a process of estimating a time duration from a changing portion of the slope of the instantaneous phase.
In another aspect of the present invention, there is provided an apparatus for detecting a delay fault in a phase-locked loop circuit, which comprises: frequency impulse applying means for applying a frequency impulse to a phase-locked loop circuit under test as the reference clock signal; transform means for transforming the waveform of a signal outputted from the phase-locked loop circuit under test to an analytic signal; estimating means for estimating an instantaneous phase of the analytic signal; and delay time measuring means for measuring a delay time from the fluctuation term of the estimated instantaneous phase.
In a preferred embodiment, the aforesaid transform means is a Hilbert pair generator, and further, there is provided means for estimating a linear phase from the estimated instantaneous phase and removing the estimated linear phase from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase.
In addition, the aforesaid delay time measuring means may be means for detecting a delay fault by comparing a time duration during which the phase-locked loop circuit stays in a state of oscillating a certain frequency with a time duration during which a fault-free phase-locked loop circuit having no delay fault present therein stays in a state of oscillating a certain frequency.
Alternately, the aforesaid delay time measuring means may be means for estimating a time duration from a changing portion of the slope of said instantaneous phase.
In a still another aspect of the present invention, there is provided a method of detecting a delay fault in a phase-locked loop circuit, which comprises the steps of: applying a frequency impulse to a phase-locked loop circuit to cause a state transition of the phase-locked loop circuit; estimating, from a signal outputted from the phase-locked loop circuit, an instantaneous period of the signal; and measuring, from the instantaneous period, a time duration during which the phase-locked loop circuit stays in a state of oscillating a certain frequency.
In a preferred embodiment, the aforesaid step of measuring a time duration is a step of measuring a time duration from a time point at which the input frequency impulse is returned to its original state until a time point at which the instantaneous period of the output signal from the phase-locked loop circuit suddenly changes.
In a further aspect of the present invention, there is provided an apparatus for detecting a delay fault in a phase-locked loop circuit, which comprises: frequency impulse applying means for applying a frequency impulse to a phase-locked loop circuit under test as the reference clock signal; estimating means for estimating, from a signal outputted from the phase-locked loop circuit, an instantaneous period of the signal; and delay time measuring means for measuring a time duration from the estimated instantaneous period.
In a preferred embodiment, the aforesaid delay time measuring means is means for measuring a time duration from a time point at which the input frequency impulse is returned to its original state until a time point at which the instantaneous period of the output signal from the phase-locked loop circuit suddenly changes.
The above and other objects, constructions, configurations and effects of the present invention will easily become apparent from the following description of the preferred embodiments with reference to the accompanying drawings.